As is shown in FIG. 1, an electronic memory device 1 includes a memory array 2 formed by a plurality of memory cells 3, which are arranged so as to define a first number N of rows and a second number M of columns. Moreover, the electronic memory device 1 includes a row decoder 4, a biasing circuit 6, a column decoder 8, a write circuit 9, and a read circuit 10, which typically include a number of amplifiers (not shown) depending on the number of columns, which are also known as “sense amplifiers”.
In addition, the electronic memory device 1 includes a number of first conductive paths WL equal to the number N of rows, these first conductive paths being known as “wordlines” and being coupled to the row decoder 4. Considering a row of memory cells 3, the corresponding wordline WL is coupled to each memory cell 3 of the row considered.
In addition, the electronic memory device 1 includes a number M of conductive connections (designated as a whole by CC), which are coupled between the biasing circuit 6 and the read circuit 10. In particular, represented in FIG. 1 are a first conductive connection, a second conductive connection, a third conductive connection, a fourth conductive connection, a fifth conductive connection, a sixth conductive connection, a seventh conductive connection, and an eighth conductive connection, designated, respectively, by CCA, CCB, CCC, CCD, CCE, CCF, CCG, and CCH.
In greater detail, in the case where the memory array 2 defines a so-called “static random-access memory” (SRAM), each conductive connection CC usually includes a first bitline BLG a second bitline BLT (FIG. 2). But the memory array 2 may have another architecture.
More in particular, the electronic memory device 1 includes, for each column of memory cells 3, a corresponding first bitline BLG and a corresponding second bitline BLT, which extend between the biasing circuit 6 and the sense amplifier corresponding to the column considered. Moreover, this sense amplifier has an output terminal, which, together with the output terminals of the other sense amplifiers, defines the output of the read circuit 10. In addition, the first and second bitlines BLG, BLT are coupled to all the memory cells 3 of the column considered. Alternatively, the memory device 1 may include hierarchal bit lines (e.g., local bit lines coupled to global bit lines).
As shown in greater detail in FIG. 2, which regards once again the case where the memory cells 3 are of a six-transistor (6T) SRAM type, each memory cell 3 is formed by a first transistor PUF and a second transistor PUT, which are generally of a P-MOS type and are known as first and second “load transistors”, and by a third transistor PDF and a fourth transistor PDT, which are generally of an N-MOS type and are known as first and second “pull-down transistors”.
In addition, each memory cell 3 includes a fifth transistor PGF and a sixth transistor PGT, which are generally of an N-MOS type and are known as first and second “selection transistors”.
In detail, the control terminal of the first load transistor PUF is coupled to the control terminal of the first pull-down transistor PDF so as to define a first node T. A first conduction terminal of the first load transistor PUF is coupled to a first conduction terminal of the first pull-down transistor PDF so as to define a second node F. A second conduction terminal of the first load transistor PUF is coupled to a third node DD, which, in use, is set at a supply voltage VDD. A second conduction terminal of the first pull-down transistor PDF is coupled to a reference voltage such as ground.
The control terminal of the second load transistor PUT and the control terminal of the second pull-down transistor PDT are both coupled to the second node F. A first conduction terminal of the second load transistor PUT and a first conduction terminal of the second pull-down transistor PDT are both coupled to the first node T. Moreover, the second conduction terminal of the second load transistor PUT is coupled to the third node DD, whilst the second conduction terminal of the second pull-down transistor PDT is coupled to a reference voltage such as ground.
The control terminals of the first and second selection transistors PGF, PGT are both coupled to the word line WL that corresponds to the memory cell 3. The first and second conduction terminals of the first selection transistor PGF are, respectively, coupled to the second node F and to the first bitline BLG of the memory cell 3 considered. The first and second conduction terminals of the second selection transistor PGT are, respectively, coupled to the first node T and to the second bitline BLT of the memory cell 3 considered.
As is known, each memory cell 3 stores a logic value (bit), which is equal to “1” or “0”. Each logic value stored corresponds to a pair of voltages of the first and second nodes T, F. For example, when the memory cell 3 stores the logic value “1”, the voltage on the first node T is high (approximately, equal to the supply voltage VDD), whereas the voltage on the second node F is low (approximately, zero); instead, when the memory cell 3 stores the logic value “0”, the voltage on the first node T is low, whereas the voltage on the second node F is high. The relations between the logic values stored and the voltages on the first and second nodes T, F may in any case be reversed. However, for reasons of simplicity, in what follows it will be assumed that the logic value “1” corresponds to a high voltage on the first node T and to a low voltage on the second node F, except where otherwise specified.
Given the above, the electronic memory device 1 further includes a controller circuit 20, which is coupled to the row decoder 4 and to the column decoder 8, respectively by means of a first electrical bus 22 and a second electrical bus 24. Moreover, the controller circuit 20 is coupled to the output of the read circuit 10, by means of a third electrical bus 26, and to the write circuit 9.
Operatively, the controller circuit 20 is able to control the row decoder 4 by sending a corresponding electrical row signal on the first bus 22. This electrical row signal is of a digital type, and hence can be represented as a sequence of logic values, which form the so-called row address. When the row decoder 4 receives at input this electrical row signal, it activates one of the wordlines WL, which corresponds to the sequence of logic values represented by the electrical row signal. In general, activation of a wordline envisages that this wordline is brought to a high voltage, close to the supply voltage VDD, the other wordlines remaining at a low voltage (e.g., zero).
Likewise, the control circuit 20 is able to control the column decoder 8 by sending a corresponding electrical column signal on the second bus 24. This electrical column signal is of a digital type, and hence can be represented as a sequence of logic values, which form the so-called column address. When the column decoder 8 receives at input this electrical column signal, it controls the read circuit 10 in such a way that the latter selects a subset of columns of the memory array 2, this subset corresponding to the column address.
In greater detail, if we designate by k the number of bits on which the column address is defined, and by n−k the number of bits on which the row address is defined, we have N=2n−k and M=2m+k. Moreover, the read circuit 10 selects, on the basis of the column address, a number 2m of columns of the memory array 2.
For example, with reference to the memory array 2 shown in FIG. 1, we have N=4, M=8, n=3, k=1 and m=2.
In addition, when the column address is, for example, equal to “0”, the read circuit 10 selects, by means of purposely provided multiplexing circuits contained within it (not shown) and controlled by the column decoder 8, the first, third, fifth, and seventh conductive paths CCA, CCC, CCE, and CCG, i.e., the corresponding columns of the memory array 2, and hence the corresponding first and second bitlines. Likewise, when the column address is, for example, equal to “1”, the read circuit 10 selects, by means of the aforementioned multiplexing circuits, the second, fourth, sixth, and eighth conductive paths CCB, CCD, CCF, and CCH, i.e., the corresponding columns of the memory array 2, and hence the corresponding first and second bitlines.
In practice, since just one wordline WL at a time can be active, on the output of the read circuit 10 a word is present, i.e., a set of 2m bit (in the case in point, four bits), formed alternatively:    in the case where the column address is equal to “0”, by the logic values stored in the memory cells of the first, third, fifth, and seventh column of the memory array 2 that are coupled to the active wordline; or else,    in the case where the column address is equal to “1”, by the logic values stored in the memory cells of the second, fourth, sixth, and eighth column of the memory array 2 that are coupled to the active wordline.
In other words, the memory array 2 corresponds to an equivalent array formed by 2n rows and by 2′ columns, which could be addressed without resorting to a column decoder, since each row would contain exclusively the bits of a corresponding word. As compared to this equivalent array, the memory array 2 presents the advantage that, considering a generic row, adjacent memory cells do not belong to one and the same word, and hence cannot be selected simultaneously by the read circuit 10. Consequently, any possible faults that involve two contiguous memory cells can cause single errors in the corresponding words, but not multiple errors.
More in particular, in order to prevent the need for resorting to logic circuits with a high number of inputs, the selection of the rows and columns of the memory array 2 does not take place in a single step. In fact, with reference, for example, to the selection of the rows, the row decoder 4 is typically of the so-called “Nin to Nout” type, with Nin and Nout respectively equal, for example, to two and four, or else to three and eight, as shown in FIG. 3, with particular reference to the “two to four” case.
In detail, the row decoder 4 includes a number of inputs equal to n−k, which are coupled to the controller circuit 20 by means of the first electrical bus 22. Purely by way of example, shown in FIG. 3 are a first input, a second input, a third input, a fourth input, a fifth input, and a sixth input, designated by A0-A5. In addition, the row decoder 4 includes a number of outputs equal to 2n−k.
In practice, the inputs of the row decoder 4 are coupled to the controller circuit 20, which, whenever it generates a row address, generates, on each input of the row decoder 4, a corresponding row-bit signal, indicating a corresponding bit of the row address. As a whole, the row-bit signals form the electrical row signal. In general, the row address and the column address can be provided to the controller circuit 20 by an external processing unit (not shown).
The row decoder 4 further includes a logic inverter for each input. With reference to FIG. 3, six inverters I0-I5 are hence present, each of which is coupled to a corresponding input from among the first, second, third, fourth, fifth, and sixth inputs A0-A5; consequently, the outputs of the logic inverters I0-I5 define, respectively, a first negated input, a second negated input, a third negated input, a fourth negated input, a fifth negated input, and a sixth negated input A0,n-A5,n.
In greater detail, the row decoder 4 further includes a plurality of input groups, each input group including four input logic gates, the latter being AND logic gates. In particular, in the example shown in FIG. 3, three input groups are present, designated respectively by Gin_1-Gin_3. Furthermore, considering i-th input group Gin_i (with 1≦i≦3), the first, second, third, and fourth input logic gates of this input group are designated, respectively, by Pin-i-0-Pin-i-3.
Considering once again the i-th input group Gin_i:    the first logic gate Pin-i-0 is coupled to the i-1-th negated input Ai-1,n and to the i-th negated input Ai,n;    the second logic gate Pin-i-2 is coupled to the i-1-th input Ai-1 and to the i-th negated input Ain; and    the third logic gate Pin-i-2 is coupled to the i-1-th negated input Ai-1,n and to the i-th input Ai; and    the fourth logic gate Pin-i-3 is coupled to the i-1-th input Ai-1 and to the i-th input Ai.
In addition, considering the i-th input group Gin_i, the output of the j-th (with 0≦j≦3) input logic gate is coupled to an intermediate line dec-i-j, also known as decoding line dec-i-j. Consequently, each input group is coupled to a corresponding group of intermediate lines dec-i-j.
The row decoder 4 further includes a plurality of output groups, each output group including four output logic gates, the latter being AND logic gates. In particular, in the example shown in FIG. 3, sixteen output groups are present, designated, respectively, by Gout_1-Gout—16 (shown in FIG. 3 are just the output groups Gout_1, Gout_2, Gout_15 and Gout_6). Furthermore, considering the h-th output group Gout_h (with 1≦h≦16), the first, second, third, and fourth output logic gates of this output group are designated, respectively, by Pout-h-0-Pout-h-3.
In detail, each output logic gate has a number of inputs equal to the number of input groups. In the example shown in FIG. 3, each output logic gate hence has a number of inputs equal to three. In addition, considering a generic output logic gate of the generic h-th output group, and designating by Num_Gin the number total of input groups, each input of the output logic gate is coupled to a corresponding intermediate line. In particular, each of these inputs is coupled to an intermediate line of a corresponding input group in such a way that there cannot be two inputs of the output logic gate that are coupled to two intermediate lines coming from one and the same input group, i.e., to two intermediate lines of one and the same group of intermediate lines.
Still more in particular, given any input group belonging to a subset S of input groups formed by all the input groups except one (in the example shown in FIG. 3, except the first input group Gin_1), each of the output logic gates of the h-th output group has an input of its own coupled to one and the same intermediate line coming from this any input group. In addition, as regards the input group not belonging to the subset S of input groups, which can be referred to also as to local-addressing group, each of the output logic gates of the h-th output group has an input of its own coupled to a corresponding intermediate line coming from the local-addressing group. In practice, the output logic gates of the h-th output group share a number of inputs equal to Num_Gin-1, whilst each of them is coupled to the local-addressing group thanks to the coupling of an input of its own with a different intermediate line coming from the local-addressing group.
In practice, the connections between the output logic gates and the subset S of input groups enable individual selection of the output groups, whilst the connections between the output logic gates and the local-addressing group enable discrimination, within a single output group, between the output logic gates of this output group.
The outputs of the output logic gates are each coupled to a corresponding wordline WL. Consequently, for each n−k-tuple of row-bit signals generated by the controller circuit 20, i.e., for each row address, the row decoder 4 activates, i.e., sets to a logic value “1”, a single output from among the outputs of the output logic gates, i.e., a single wordline.
This being said, in general, the detection of the faults within electronic memory devices is entrusted to the use of the so-called “error-correction codes” (ECCs). More in particular, the error-correction codes perform the function of guaranteeing a certain tolerance in regard to transient errors.
In practice, the controller circuit 20, in addition to generating column and row addresses, and further electrical signals designed to control the operations of reading and writing of the memory array 2, is provided with an ECC module 30, which operates as shown in FIG. 4. On the other hand, the ECC module can also be external to the electronic memory device 1.
In detail, the ECC module 30 generates (block 40) an information word, formed by a number 2z of bits, with z<m. Next, the ECC module 30 selects a row address and a column address (blocks 42 and 44).
Next, the ECC module 30 generates (block 46) a code word, on the basis of the information word and of a global address formed by the row and column addresses selected. In particular, the code word is formed by 2m bits and is obtained by using an encoding according to an error-correction code, such as for example a Hamming code (n+2m+c, n+2m, d) with c=redundancy bits and d=Hamming distance.
The ECC module hence performs (block 48) a write cycle, controlling the write circuit 9 and the row and column decoders 4, 8 so as to write the code word in the memory array 2. In particular, the 2m bits of the code word are written in a subset of memory cells 3 of the row indicated by the row address selected, this subset being a function of the column address selected. In brief, it is common to refer to this write operation as writing of the code word at the global address. For example, with reference to FIG. 1, where k=1 and n=3, the global address occupies n bits, of which two (for example, the two most significant bits) indicate one of the four rows of the memory array 2, whilst one bit (for example, the least significant bit) discriminates between even columns and odd columns of the memory array 2. For example, in the case where the least significant bit is equal to “0”, the first, third, fifth, and seventh columns are selected, whereas, in the case where the least significant bit is equal to “1”, the second, fourth, sixth, and eighth columns are selected.
In practice, the information content associated with the code word is the information word, which occupies a number of bits lower than the number 2m of columns of the aforementioned equivalent array.
Next, the ECC module 30 performs (block 50) a cycle of reading at the global address; i.e., it selects the 2m bits stored in a subset of memory cells of the row designated by the aforementioned row address selected, this subset being a function of the aforementioned column address selected. In this way, the ECC module 30 accesses the same memory cells that it accessed during the previous step of writing of the code word, and reads a word stored therein. In general, between the operations of block 48 and the operations of block 50, other operations can be executed, such as for example operations of writing and reading at addresses different from the global address.
Next, the ECC module 30 performs (block 52) a decoding of the word stored on the basis of the error-correction code and of the global address. In this way, the ECC module 30 is able to detect and, to a certain extent, correct possible errors (i.e., erroneous bits) within the word stored. In particular, in the case where the error-correction code is of the so-called “single error correction—double error detection” (SEC/DEC) type, the ECC module 30 is able to correct a single error present in the word stored, as well as to detect, but not correct, a double error present in the word stored, as well as possibly some higher-order errors.
In general, the errors can be caused either by faults of the memory array 2, and in particular in the portion of memory array occupied by the word stored, or by faults of the row decoder 4 and/or of the column decoder 8. Consequently, the errors can be generated during storage of bits in single memory cells 3, or else during addressing, i.e., on account of incorrect accesses.
In particular, in the case of faults of the memory array 2, these can be temporary, such as, for example, in the case where a temporary flip of the bit stored in a memory cell 3 occurs. For example, after the code word has been written in the memory array 2, this bit flip can be induced by disturbance such as the impact with alpha particles or neutrons. Furthermore, this flip can be removed by means of a subsequent rewriting.
The faults of the memory array 2 may moreover be permanent, such as, for example, in the case where a memory cell stores a fixed bit, irrespective of the bits that the controller circuit 20 attempts to write in this memory cell. In this case, if this memory cell is referred to as “faulty cell”, the error presents, and is hence detectable, only in the case where the bit of the code word to be stored in the faulty cell is different from the aforementioned fixed bit.
Irrespective of the temporary or permanent nature of the faults of the memory array 2, each of them generally causes not more than one error per stored word. In other words, with reference to the aforementioned stored word, a fault of the memory array 2 can cause this stored word to differ by not more than one bit from the code word written at the global address during the operations of block 48.
In particular, the likelihood of each fault of the memory array 2 causing more than one error is reduced as multiplexing increases, i.e., as the value of k increases. In fact, as the value of k increases, pairs of memory cells for one and the same code word depart from one another. In this connection, as mentioned previously, given two successive memory cells for one and the same code word, set between them is a number k of memory cells for different code words.
In the case of faults of the row decoder 4 and/or of the column decoder 8, these are typically of a permanent nature, since they are caused, in general, by couplings between adjacent conductive paths, or else by erroneous connections of the conductive paths, such as for example erroneous connections to the supply or to ground. In these cases, it happens that, given an operation of writing of a given code word at a given address (the given code word hence being a function, not only of a corresponding information word, but also of the given address), this code word is written at a different address. Consequently, during the operations of decoding of the word stored at this different address, the ECC module detects the presence of an error. In fact, in the absence of errors in the memory array, the word stored coincides with the given code word; however, it is in fact stored at an address different from the given address.
Since each fault causes incorrect accesses to the memory array 2, each fault can cause a high number of errors. Consequently, with reference once again to the code word, in the case of a fault in the row decoder 4 and/or in the column decoder 8, it is possible for the word stored to contain multiple errors. These faults can hence have very serious effects as compared to faults of the memory array 2.
Given this, in the case where the ECC module 30, following upon the operations of block 52, detects the presence of at least one error in the word stored, it generates (block 54) an error signal indicating the presence of at least one error and the possible correction of the error by the ECC module 30 itself.
In general, as mentioned previously, the implementation of error-correction codes enables detection and, in some cases, correction, of errors, whether these be due to faults of the memory array 2 or else to faults of the row decoder 4 and/or of the column decoder 8. However, the use of the error-correction codes does not enable discrimination between faults of the memory array 2 and faults of the row decoder 4 and/or of the column decoder, and in particular does not enable detection of permanent faults of an address decoder.